任职要求：
月薪范围（25000-50000 元/月，base 合肥）
岗位职责：
1、Working with ASIC design and architecture teams to understand the functionality of logic blocks；
2、Develop and drive verification plans；
3、Generate constrained random and directed tests to implement verification plan；
4、Run simulations and debug issues；
5、Create verification test bench components to monitor and check design；
6、Create functional coverage points, analyze coverage, and enhance test coverage.
任职资格：
1、Familiar with Verilog RTL and System Verilog；
2、Familiar with C/C++；
3、Familiar with UVM verification methodology and flow is plus；
4、Familiar with assertion design is plus；
5、Experience in Verdi/VCS/UPF is plus；
6、Familiar with UFS Unipro is plus；
7、Familiar with eMMC is plus.
